1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit having means for suppressing a temperature-related variation in a threshold level.
2. Description of the Related Circuit
Generally, an integrated circuit formed on a semiconductor chip is composed of an input circuit, an internal circuit and an output circuit, as shown in FIG. 1A. A common power supply line L is provided in common to the input circuit, the internal circuit and the output circuit. Electricity is supplied to the input circuit, the internal circuit and the output circuits via a pair of power supply lines, one of which is maintained at a high potential and the other one of which is maintained at a low potential. The common power supply line L shown in FIG. 1A is one of the pair of power supply lines.
Generally, the output circuit consumes much more energy than the input circuit and the internal circuit. Thus, when a large number of internal elements, such as transistors, executes a switching operation, a large variation occurs in current passing through the output circuit. This current variation causes a change in potential of the power supply line L. This change in potential of the power supply line L causes various problems in the input circuit and/or the internal circuit.
When the input circuit is composed of CMOS (Complementary Metal Oxide Semiconductor) elements, it includes a CMOS inverter. When the input circuit is composed of a BiCMOS (Bipolar-Metal Oxide Semiconductor) circuit, the input circuit includes a CMOS inverter in the first stage of the BiCMOS circuit.
The CMOS inverter has a threshold level Vth. When an input signal has a level higher than the threshold level Vth, the CMOS inverter outputs a low-level signal. When the input signal has a level lower than the threshold level Vth, the CMOS inverter outputs a high-level signal. The CMOS inverter is composed of a p-channel MOS transistor (hereafter simply referred to as a pMOS transistor) and n-channel MOS transistor (hereafter simply referred to as an nMOS transistor), both of which are connected in series.
FIG. 1B is a graph of drain voltage (V.sub.DD) vs. drain current (I.sub.D) characteristics of the pMOS and nMOS transistors. V.sub.i1 through V.sub.i5 are gate voltages of the pMOS and nMOS transistors. Reference numerals 1 through 5 indicate cross points where the V.sub.DD -I.sub.D characteristics of the pMOS transistor cross those of the nMOS transistor. At cross point 1, the nMOS transistor is OFF, and the pMOS transistor is ON. At cross point 2, the nMOS transistor operates in a saturated area, and the pMOS transistor operates in a linear area. At cross point 3, both the nMOS and pMOS transistors operate in respective saturated areas. At cross point 4, the nMOS transistor operates in a linear area, and the pMOS transistor operates in the saturated area. At cross point 5, the nMOS transistor is ON, and the pMOS transistor is OFF. The threshold level Vth corresponds to a drain voltage obtained at cross point 3. That is, the threshold level Vth corresponds to an identical drain voltage of the pMOS and nMOS transistors when these transistors are in the saturated areas. When the nMOS and pMOS transistors have good complementary characteristics (for example, when .beta.n=.beta.p and Vthn=Vthp where .beta.n and .beta.p are, respectively, current transfer ratios of the nMOS and pMOS transistors and Vthn and Vthp are respectively the threshold levels of the nMOS and the pMOS transistors), the threshold level Vth of the CMOS inverter is equal to V.sub.DD /2.
The drain current I.sub.D of a MOS transistor when it is in the saturated area can be written as follows: EQU I.sub.D =.beta.(Vin-Vth).sup.2 /2 EQU .beta.=.mu.CoxW/L
where .beta. is the current transfer ratio of the MOS transistor, Vin is the input voltage applied to the MOS transistor, .mu. is the mobility, Cox is the thickness of an oxide film, W is the width of the gate of the MOS transistor, and L is the length thereof.
The mobility .mu. of the MOS transistor decreases as its temperature increases. Hence, as temperature increases, both the current transfer ratio .beta. and the drain current I.sub.D decrease. Since the mobility of holes is much greater than that of electrons, diminutions in .mu., .beta. and I.sub.D of the pMOS transistor due to temperature variations are greater than those of the nMOS transistor. Thus, as shown in FIG. 1C, the cross point 3 moves to a cross point 3', and thus, the threshold level Vth of the CMOS inverter increases. This change in the threshold level Vth causes malfunctions of the input circuit.